The present invention relates to a semiconductor fabricating method, and, more particularly, to a method for fabricating a capacitor.
Recently, as an integration of memory devices increases due to demands for micro-sized semiconductors, a unit cell region decreases and an operational voltage decreases. However, even though the cell region is reduced in size, the memory device still requires a charge capacitance of at least 25 fF/cell to prevent soft errors from occurring and to prevent a refresh time from being shortened.
A high dielectric layer having a high dielectric constant, such as a hafnium oxide (HfO2) layer and a zirconium oxide (ZrO2) layer, has been developed to ensure an equivalent oxide thickness (TOX) within a range of about 10±2 Å. Thus, a metal-insulator-metal (MIM) capacitor based on a concave-shaped storage node structure has been employed for 80 nm-level dynamic random access memory (DRAM) devices. However, since semiconductor DRAM devices employing a metallization process of less than a 70 nm-level cannot sufficiently ensure an effective area of about 0.84 μm2/cell in the concave-shaped storage node structure, the semiconductor DRAM devices cannot obtain a cell capacitance over 25 fF/cell. Accordingly, the MIM capacitor having a cylindrical structure is employed in 60 nm-level devices.
FIG. 1 illustrates a conventional storage node having a cylindrical structure.
A plurality of cylindrical storage nodes 12 are formed over a lower layer 11. In order to fabricate the cylindrical storage nodes 12, a wet etching process (referred to as a full dip out process) using a sacrificial layer and a drying process are performed. When a ratio of a height H of the storage node 12 to a width W of the storage node 12 exceeds approximately 12:1, water marks existing between neighboring storage nodes may be evaporated in the drying process after the wet etching process, resulting in a leaning phenomenon.
Since a dual bit failure results due to a storage node bridge (SN bridge) caused by the leaning phenomenon as shown in FIG. 2, a method for increasing the height of the storage node to obtain a charge capacitance of more than 25 fF/cell is limited.
FIG. 2 illustrates a storage node bridge formed in a conventional method for forming cylindrical storage nodes. The storage node bridge is caused due to the leaning phenomenon between neighboring storage nodes. Accordingly, an alternative technology capable of overcoming the above limitation is required in an under 60 nm-level DRAM.